The present invention relates to a decoupling circuit and a semiconductor integrated circuit, and more particularly to a decoupling circuit and a semiconductor integrated circuit, which can switch a capacitance value.
With an increase in the operating speed of a semiconductor integrated circuit, an on-chip decoupling capacitance for reducing a power supply noise is required. A power supply noise amount and a resonance frequency in question are determined according to a board, a package, and a chip. However, it is difficult to estimate the power supply noise amount and the resonance frequency with precision through simulation when the chip is designed. Also, in the chip that operates at plural frequencies, there is a risk that any operating frequency coincides with a resonance frequency. Hence, for the purpose of preventing the operating frequency from coinciding with the resonance frequency, the resonance frequency needs to be controlled.
An example of the above-mentioned on-chip decoupling capacitance is disclosed in Japanese Patent Laid-Open No. 2003-86699. FIG. 5 is a circuit diagram of a decoupling capacitance 300 disclosed in Japanese Patent Laid-Open No. 2003-86699. As illustrated in FIG. 5, the decoupling capacitance 300 includes an n-type MOS transistor 11 and a p-type MOS transistor 12. A source electrode of the n-type MOS transistor 11 is coupled to a ground line, a source electrode of the p-type MOS transistor 12 is coupled to a power supply line, a drain electrode of the n-type MOS transistor 11 is coupled to a gate electrode of the p-type MOS transistor 12, and a drain electrode of the p-type MOS transistor 12 is coupled to a gate electrode of the n-type MOS transistor 11.
Subsequently, the operation of the decoupling capacitance 300 will be described. The respective nodes of the gate electrodes of the n-type MOS transistor 11 and the p-type MOS transistor 12 are floating. However, the node of the gate electrode of the n-type MOS transistor is determined to a power supply line potential, and the node of the gate electrode of the p-type MOS transistor is determined to a ground line potential, by leak currents of the respective transistors in a short time after a power supply turns on. Accordingly, both of those transistors turn on, and are rendered conductive.
That is, in the decoupling capacitance 300, a series coupling of an on-resistance of the n-type MOS transistor and a gate capacitance of the p-type MOS transistor, and a series coupling of an on-resistance of the p-type MOS transistor and a gate capacitance of the n-type MOS transistor are formed between the power supply line and the ground line.
In the decoupling capacitance 300, each of the n-type MOS transistor and the p-type MOS transistor functions as both of the gate capacitance and an ESD protection resistance, and an area for newly forming an ESD protection resistance is not required. Therefore, the decoupling capacitance 300 is excellent in area efficiency.
Japanese Patent Laid-Open No. 2003-86699 discloses that the decoupling capacitance 300 can provide a decoupling capacitance that has an ESD resistance, is excellent in the area efficiency, and does not increase the number of processes.
Also, a configuration of a cross coupling type decoupling capacitor for the purpose of improving electrostatic discharge withstand voltage characteristics has been known (Japanese Patent Laid-Open No. 2009-246062). Further, there has been known a technique by which an impedance of a power supply circuit is controlled according to a waveguide frequency of the semiconductor integrated circuit (Japanese Patent Laid-Open No. 11-7330).